Marc Majoral

Ico_CTTC

Navigation & Positioning (N&P)

Msc , Researcher

Phone: +34 93 645 29 00

Marc Majoral (Sabadell, 1974) received his M.S. degree in Electrical Engineering from the Polytechnic University of Catalonia (UPC) in 1998. He also holds a Master degree in Research on Information and Communications Technologies (MERIT) from the UPC since 2014.
Marc joined CTTC in January 2007. In the period 1999 – 2006 he worked in the Cochlear Technology Centre in Belgium, where he implemented signal processing strategies for cochlear implants. In 1999 he worked in the Signal Theory and Communications department in the Polytechnic University of Catalonia (UPC), where he was involved in Digital Signal Processing (DSP) programming for mobile communications. In 1998 he worked as a software developer in Bull-SP, Barcelona, Spain. During 1997 he was granted an undergraduate scholarship in the IT department in Hewlett-Packard, Sant Cugat del Vallès, Spain.

Marc works on the design and development of real-time signal processing communication devices, computationally intensive DSP algorithms, Software-Defined Radio (SDR) systems, Field Programmable Gate Array (FPGA) – based systems and embedded systems. He has been involved in various industrial projects (GNSS_IN_SPACE, RADPARK, Coupled-ETC, LTE LISTEN MODE – TDD-LTE Physical Layer, ULTRAMUMO, MUMO and R@ILNET) and public funded projects (ARISTIDES, AUDITOR). In the Coupled-ETC project he also worked as WP leader for the implementation tasks. In 2017 and 2018 he participated as a CTTC internship supervisor for the The Overseas Internship Scheme (OIS) summer training programme by the CityU in Hong Kong. He is also involved in some research dissemination activities: presentation of the GNSS_IN_SPACE Project at ESA, in SEFUW: SpacE FPGA Users Workshop, 4th Edition (2018), presentation of a candidate project in the IESE Barcelona Technology Transfer Group (IESE-BTTG 2017).

Summary of the project contributions:

GNSS_IN_SPACEII: design, implementation, testing and verification.
GNSS_IN_SPACE (ESA, industry): design, implementation, testing and verification of an FPGA architecture for an All-Programmable System-On-Chip based Space GNSS Receiver prototype.
RADPARK (industry): contribution to the analysis of various HW alternatives for the project.
Coupled-ETC (ESA, industry): WP leader of the implementation tasks and developer. Design, development, system integration, testing and verification of an FPGA-based TT&C Coupled Enhanced Turbo Codes Demodulator and Decoder.
LTE LISTEN_MODE (industry): Design, implementation and testing.
ULTRA high capacity multicarrier modulation modem for power line communications (ULTRAMUMO, industry): design, implementation, testing and verification. Coordination of the implementation activities.
MUMO (industry): design, implementation, testing and verification.
AUDITOR (European): design, implementation, testing and verification of an FPGA-based GNSS Receiver prototype for precision agriculture.
R@ILNET: extention of the FPGA design in order to increase the flexibility of the DVBT phy layer.

Summary of his involvment in project proposals:

ARISTIDES (2019): technical contribution.
GNSS_IN_SPACE (2017): technical contribution
RADPARK (2017): technical contribution
REVIVE-A European project (2016): technical contribution
UpSTART (2016): technical contribution.
Coupled-ETC (2012): technical contribution
ULTRAMUMO (2012): technical contribution
SDR Hardware Platform Development (2011): technical contribution.
DEMUMO (2011): technical contribution.
LTE LISTEN MODE (2010): technical contribution
MUMO (2007): technical contribution
ORCID ID: https://orcid.org/0000-0001-6161-6747

Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform
SENSORS. Vol. 24. No. 5. January 2024.
Majoral M., Arribas J., Fernández-Prades C.
10.3390/s24051416 Google Scholar
A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers
SENSORS. Vol. 23. No. 23. January 2023.
Majoral, M, Fernández-Prades, C, Arribas, J
10.3390/s23239483 Google Scholar
Implementation of a GNSS Rebroadcaster in an All-Programmable System-On-Chip Platform
2022 10th Workshop On Satellite Navigation Technology, Navitec 2022. January 2022.
Majoral M., Arribas J., Fernandez-Prades C.
10.1109/NAVITEC53682.2022.9847537 Google Scholar
A Software-Defined Spaceborne GNSS Receiver
2018 9th Esa Workshop On Satellite Navigationtechnologies And European Workshop On Gnss Signals And Signal Processing (navitec). January 2018.
Fernandez-Prades, C, Arribas, J, Majoral, M, Ramos, A, Vila-Valls, J, Giordano, P
Google Scholar
A software-defined spaceborne gnss receiver
ESA Workshop on Satellite Navigation Technologies and European Workshop on GNSS Signals and Signal Processing. Vol. 2018-December. January 2018.
Ferná Ndez-Prades C., Arribas J., Majoral M., Ramos A., Vilà-Valls J., Giordano P.
10.1109/NAVITEC.2018.8642697 Google Scholar
Implementation of GNSS receiver hardware accelerators in all-programmable system-on-chip platforms
Proceedings Of The 31st International Technical Meeting Of The Satellite Division Of The Institute Of Navigation, Ion Gnss+ 2018. pp. 4215-4230 January 2018.
Majoral M., Fernández-Prades C., Arribas J.
10.33012/2018.16082 Google Scholar
An asymptotic approach to parallel equalization of filter bank based multicarrier signals
IEEE TRANSACTIONS ON SIGNAL PROCESSING. Vol. 61. No. 14. pp. 3592-3606 January 2013.
Mestre, X, Majoral, M, Pfletschinger, S
10.1109/TSP.2013.2261297 Google Scholar
On Implementation Requirements and Performances of Q-Learning for Self-Organized Femtocells
Ieee Globecom Workshops. pp. 231-236 January 2011.
Galindo-Serrano, A, Giupponi, L, Majoral, M
Google Scholar
On implementation requirements and performances of Q-Learning for self-organized femtocells
2011 Ieee Globecom Workshops (gc Wkshps). pp. 231-236 January 2011.
Galindo-Serrano A., Giupponi L., Majoral M.
10.1109/GLOCOMW.2011.6162443 Google Scholar
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