ITERATE - dIgiTal prE-distortion foR multi-AnTenna wavEforms

The project forms part of a 5G BS product development and consists of implementing in field programmable gate array (FPGA) devices the digital front end (DEF) of a remote radio head (RRH) for three different downlink (DL) transmit chains. The three variations of the RRH transmitter feature eight antenna elements. Transmitter 1 has an 80 MHz bandwidth (BW) and the developed RRH DFE will be validated using the following building blocks: data generation and common public radio interface (CPRI) transmission emulating the baseband unit (BBU), CPRI reception, digital up-conversion (DUC), crest factor reduction (CFR) and digital pre-distortion (DPD). Transmitter 2 has a 200 MHz BW and the developed RRH DFE will be validated using the following building blocks: data generation and CPRI transmission, CPRI reception, DUC and digital mixing, CFR and DPD. Finally, Transmitter 3 has a 400 MHz BW developed RRH functionality will be validated using the following building blocks: data generation and CPRI transmission, CPRI reception, DUC and digital mixing. Gi9ven the previous specification the FPGA design will have to feature beyond the state-of-the-art performance.